1. Field of the Invention
This invention relates generally to probe card assemblies used in the testing of integrated circuits and more specifically to a probe card assembly with a coplanar daughter card.
2. Background
A probe card assembly is used to test semiconductor devices during manufacture to determine whether the semiconductor devices function properly. As is known, a semiconductor tester generates test signals to be input into the semiconductor device. The semiconductor tester then monitors and analyzes signals generated by the semiconductor device in response to the test signals to determine whether the semiconductor device is functioning correctly. Generally speaking, a probe card assembly acts as an interface between the semiconductor tester and the semiconductor device, routing the test signals from the semiconductor tester to specific input points on the semiconductor device, and also routing signals generated by the semiconductor device in response to the test signals back to the semiconductor tester.
FIGS. 1A-1C illustrate a typical prior art test arrangement. As shown, a typical probe card assembly 100 includes a printed circuit board 102, which is usually round and contains a pattern of tester contacts 130 for connecting to a semiconductor tester 120. It should be noted that the contacts 130 are typically formed all around the printed circuit board 102; in FIG. 1B only a few of such contacts 130 are shown. The semiconductor tester may include pogo-style pins 122 that contact the tester contacts 130. Rather, than pogo-style pins, however, the semiconductor tester 120 may use any mechanism for establishing a temporary electrical connection with the tester contacts 130. A probe head assembly 106 is attached to printed circuit board 102. The probe head assembly 106 includes probes 108 for contacting the semiconductor devices being tested (not shown). The probe head assembly 106 is typically attached to the printed circuit board 102 via mechanism 104.
As shown in FIG. 1C (which illustrates a cross-section of the probe card assembly 100 shown in FIG. 1B) electrical traces 150 on or within the printed circuit board 102 connect the tester contacts 130 to the probe head assembly 106 and ultimately to probes 108. Thus, electrical paths between inputs and outputs (not shown) on the semiconductor tester 120, on one hand, and the probes 108, on the other hand, are established. As also shown in FIG. 1C, a typical probe head assembly 106 consists of a space transformer 156 that is connected to the printed circuit board 102 via connections 152. The connections 152 may be, for example, solder ball connections or contact pins soldered to the printed circuit board 102, the space transformer 156, or both. Traces 150 on or within the printed circuit board 102 connect the tester contacts 130 to the connections 152, and traces 154 on or within the space transformer 156 connect the connections 152 to the probes 108.
FIG. 2 illustrates another type of probe head assembly 106, an example of which is described in detail in U.S. Pat. No. 5,974,662, assigned to the current assignee of the instant application and incorporated herein by reference in its entirety. The printed circuit board 202 of FIG. 2 may be similar or even identical to the printed circuit board 102 of FIGS. 1A-1C. The printed circuit board 202 includes tester contacts 230 for connecting to a semiconductor tester (not shown). The tester contacts 230 are connected to probe head contacts 210 in a manner similar to which the tester contacts 130 are connected to connections 152 in FIG. 1C. (These connections are not shown in FIG. 2 because FIG. 2 is not a cross-sectional view.)
In FIG. 2, the probe head assembly 106 includes an interposer 216 and a space transformer 224. Resilient interconnection elements 212 provide electrical connections between contacts 210 on the printed circuit board 202 and contacts 214 one side of the interposer 216. Similarly, resilient interconnection elements 220 provide electrical connections between contacts 218 on the other side of the interposer 216 and contacts 222 on the space transformer. Internal connections (not shown) within the interposer 216 connect contacts 214 on one side of the interposer to contacts 218 on the other side of the interposer. Similarly, internal connections (not shown) within space transformer 224 connect contacts 222 to probes 226. Probes 226, which directly contact test points on the semiconductor being tested, may be resilient contacts, such as those described in U.S. Pat. Nos. 5,476,211, 5,917,707, and 6,184,053 B1, all assigned to the currently assignee of the instant application, and all incorporated herein by reference in their entirety. Likewise, resilient interconnection elements 212 and 220 may be resilient contacts.
It should be noted that no particular type of probe head assembly 106 is critical to the instant invention. Indeed, the instant invention may be used in connection with either the type of probe head assembly 106 described in FIGS. 1A-1C or FIG. 2 or any other type of probe head assembly suitable for probing semiconductor devices.
Generally speaking, the pattern of test signals generated by the semiconductor tester 120 must be unique to the semiconductor device being tested. Semiconductor testers, however, are typically designed to output a limited number of test patterns. This means that the test signals output by the semiconductor tester 120 often must be processed by circuitry located on the printed circuit board 102 or 202 so that the test signals delivered to the semiconductor device at the probes 108 or 226 are as required by the semiconductor device. That is, the test signals generated by the semiconductor tester 120 must be enhanced or customized to suit the particular test needs of the semiconductor device. Similarly, signals output by the semiconductor device in response to the test signals may need to be processed by circuitry located on the printed circuit board 102 or 202 before being passed back to the semiconductor tester 120. Again, the signals generated by the semiconductor device must be customized to the particular test requirements of the semiconductor device.
Such circuitry cannot be located on the printed circuit board 102 in such a way as to interfere with the connections between the tester contacts 130 on the printed circuit board and the semiconductor tester's 120 pogo pins 122. As shown in FIG. 3A, the tester contacts 130 are typically located in an outer area 140 of the printed circuit board 102. This means that the processing circuitry 302 is typically located entirely within an inner area 142 of the printed circuit board. Indeed, the greater the number of connections between the semiconductor tester 120 and the probe card assembly 100, the less space there is within the outer area 140 of the printed circuit board 102 for things such as processing circuitry (not shown). In recent years, the number and density of probes 108 on the probe head assembly 106 has steadily increased, which has caused a corresponding increase in the amount of test data sent to and received from the probes 106. Of course, an increasing amount of data flowing between the semiconductor tester 120 and the probes 106 requires an increasing number of connections between the semiconductor tester 120 and the printed circuit board 102.
As shown in FIG. 3B, some traces 150a may connect tester contacts 130 directly to the probe card assembly 106. Other traces 150b, however, may connect tester contacts 130 to processing circuitry 302, which in turn is connected to probe head assembly 106 by traces 150c. It should be understood that the probe head assembly 106 shown in FIGS. 3A and 3B can be any probe head assembly suitable for contacting a semiconductor device under test, including but not limited to the probe head assemblies 106 illustrated in FIGS. 1A-1C and FIG. 2.
In recent years, the size of probe head assemblies has steadily grown. As should be apparent, the larger the probe head assembly, the less room there is on the printed circuit board for processing circuitry. Therefore, there is a need for a method and apparatus for locating processing circuitry on a probe card assembly in such a way as to allow for the use of larger probe head assemblies while not interfering with connections between the semiconductor tester and the probe card assembly.